For rapid real-time signal processing, a computer system, especially a multi-processor system, is often configured with multiple processing units for controlling and quickly processing data simultaneously. The processing units of the system may comprise of various devices, such as Central Processing Unit (CPU), Digital Signal Processor (DSP) and memories. Similarly for on-chip systems, mass devices are integrated into a common chip. In consideration of die size and cost, such a system shares resources among multiple processing units by using the same bus. Therefore, between mass devices, a device which transmits a request to the bus asking for the data transferring is called a master device; a target device, which will receive the data transferring from the master device, is called a slave device. In a multiple devices system, the number of master devices and slave devices may be above two, if these devices need using a system bus at the same time may result in data conflict. For avoiding the data conflicting issue, only one master device is permitted to use the system bus at a time. A master device transmits a bus usage request at first, and will not control the bus until it is arbitrated and authorized by the bus arbiter. Secondly the master device send out addresses and data information, in order to write the data to specified addresses of the slave devices or read data from specified addresses of the slave devices. The bus usage will not be freed until the data transference between the master device and the slave devices is finished.
In general, the master device always transmits a single address at a time, and correspondingly, only allowed to transfer single data to the same address of the same slave device. When the master device needs to transfer data to different addresses of the same slave device or to different slave devices, it has to transmit new bus usage requests and is arbitrated again by the bus. For instance, a Chinese patent (patent No. 86108261) discloses such a data transfer system. When the system transfers data from I/O (Input/Output) device to a main memory, the I/O device 16 needs to transmit data to an input buffer 30 by a data bus 40, and then the data are stored in the addresses of the buffer specified by an address register. At that time, the address register 28 and a count register will refresh respectively. If the data are written in a positive direction, the address register 28 pluses 1 and the count register substrates 1; and if the data are read in a negative direction, the address register 28 substrates 1 and the count register still substrates 1. In this kind of system, when the master device needs to transmits multiple data continuously, the system will take several arbitration periods to complete all the data transfer processes from the time a first bus usage request is transmitted, resulting in some defects, such as low efficiency of the bus and long latency.
Burst-type data transfer method improves the single-type data transfer system. The burst-type data transfer is able to transfer a lot of data continuously at a time, but still has drawbacks. Data transferred by the burst-type data transfer system are required to be in continuous addresses. Namely, when a master device performs a read operation, data should be read from sequential addresses of the same slave device; when a master device performs a write operation, data should be written to sequential addresses of the same slave device. Once the data need to be transferred to discontinuous addresses, the master device has to transmit another bus usage request, and let the bus arbiter arbitrates again.
To overcome above deficiencies, the instant invention provides a new bus system, in which data are transferred in form of stream bursts.